use WORK.all;

entity TEST_BENCH is
end TEST_BENCH;

architecture SHIFTER_TEST of TEST_BENCH is
  signal RUN, CLK : BIT;
  signal PG : BIT_VECTOR(3 downto 0);
  signal S0 : BIT_VECTOR(3 downto 0) := "0000";
  signal S1 : BIT_VECTOR(3 downto 0) := "0101";
  signal S2 : BIT_VECTOR(3 downto 0) := "1010";
  signal S3 : BIT_VECTOR(3 downto 0) := "1111";
  signal Z : BIT_VECTOR(3 downto 0);

begin
  L1: entity shifter(alg)
    generic map(2 ns)
    port map(S1, SR => PG(3), SL => PG(2), IL => PG(1),
             IR => PG(0), DATA_OUT(3) => Z(3),
             DATA_OUT(2) => Z(2), DATA_OUT(1) => Z(1),
             DATA_OUT(0) => Z(0));

  L2 : entity pulse_gen(alg)
    generic map(4, 20 ns)
    port map(RUN, PG);

  process
  begin
    RUN <= '1', '0' after 10 ns;
    wait;
  end process;
end SHIFTER_TEST;