use WORK.all;

entity TEST_BENCH is
end TEST_BENCH;

architecture SHIFTREG_TEST of TEST_BENCH is
  signal RUN, CLK : BIT := '0';
  signal PG : BIT_VECTOR(4 downto 0);
  signal S0 : BIT_VECTOR(3 downto 0) := "0000";
  signal S1 : BIT_VECTOR(3 downto 0) := "0101";
  signal S2 : BIT_VECTOR(3 downto 0) := "1010";
  signal S3 : BIT_VECTOR(3 downto 0) := "1111";
  signal Z : BIT_VECTOR(3 downto 0);

begin
  L1: entity shiftreg(df)
    generic map(2 ns)
    port map(S1, CLK, LOAD => PG(4), SR => PG(3),
             SL => PG(2), IL => PG(1), IR => PG(0), Q => Z);

  L2 : entity pulse_gen(alg)
    generic map(5, 20 ns)
    port map(RUN, PG);

  process
  begin
    RUN <= '1', '0' after 10 ns;
    wait;
  end process;

  process(CLK)
  begin
    CLK <= not CLK after 10 ns;
  end process;
end SHIFTREG_TEST;