use WORK.all;
library ieee;
use ieee.std_logic_1164.all;

entity TEST_BENCH is
end TEST_BENCH;

architecture RAM_TEST of TEST_BENCH is
  signal RUN_DATA : std_logic;
  signal RUN_ADDRESS : std_logic;
  signal PG_ADDRESS : std_logic_vector(4 downto 0);
  signal PG_DATA : std_logic_vector(3 downto 0);
  signal RD : std_logic;
  signal WR : std_logic;
  signal NCS : std_logic;

begin
  L1: entity ram(simple)
    generic map(2 ns, 2 ns)
    port map(PG_DATA, PG_ADDRESS, RD, WR, NCS);

  L2 : entity pulse_gen(alg)
    generic map(5, 20 ns)
    port map(RUN_ADDRESS, PG_ADDRESS);

  L3 : entity data_pulse_gen(alg)
    generic map (4, 40 ns)
    port map(RUN_DATA, PG_DATA);

  process
  begin
    RUN_ADDRESS <= '1', '0' after 10 ns, '1' after 700 ns, '0' after 710 ns;
    RUN_DATA <= '1', '0' after 10 ns;
    WR <= '1', '0' after 641 ns;
    RD <= '0', '1' after 642 ns;
    NCS <= '0', '1' after 1500 ns;
    wait;
  end process;

end RAM_TEST;