--use work.PRIMS.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;

entity RAM is
  generic (RDEL,DISDEL: TIME);
  port (DATA: inout std_logic_vector(3 downto 0);
        ADDRESS: in std_logic_vector(4 downto 0);
        RD,WR,NCS: in std_logic);
end RAM;

architecture SIMPLE of RAM is
  type MEMORY is array(0 to 31) of std_logic_vector(3 downto 0);
begin
  process(RD,WR,NCS,ADDRESS,DATA)
    variable MEM: MEMORY;
  begin
    if NCS='0' then
      if RD='1' then
        DATA <= MEM(to_integer(ADDRESS)) after RDEL;
      elsif WR='1'then
        MEM(to_integer(ADDRESS)) := DATA;
      end if;
    else
      DATA <= "ZZZZ" after DISDEL;
    end if;
  end process;
end SIMPLE;
--Figure 4.37 RAM primitive.