use WORK.all;

entity TEST_BENCH is
end TEST_BENCH;

architecture MUX4_TEST of TEST_BENCH is
  signal RUN, CLK : BIT;
  signal PG : BIT_VECTOR(1 downto 0);
  signal S0 : BIT_VECTOR(3 downto 0) := "0000";
  signal S1 : BIT_VECTOR(3 downto 0) := "0101";
  signal S2 : BIT_VECTOR(3 downto 0) := "1010";
  signal S3 : BIT_VECTOR(3 downto 0) := "1111";
  signal Z : BIT_VECTOR(3 downto 0);

begin
  L1: entity four_to_1_mux(df)
    generic map(2 ns)
    port map(S0, S1, S2, S3, PG,  Z);

  L2 : entity pulse_gen(alg)
    generic map(2, 20 ns)
    port map(RUN, PG);

  process
  begin
    RUN <= '1', '0' after 10 ns;
    wait;
  end process;
end MUX4_TEST;