use WORK.all;

entity TEST_BENCH is
end TEST_BENCH;

architecture LATCH_TEST of TEST_BENCH is
  signal RUN, CLK : BIT := '0';
  signal PG : BIT_VECTOR(1 downto 0);
  signal S : BIT_VECTOR(7 downto 0) := "01011010";
  signal Z : BIT_VECTOR(7 downto 0);

 begin
  L1: entity latch(dflow)
    generic map(2 ns)
    port map(S, CLK, Z);

  process
  begin
    RUN <= '1', '0' after 10 ns;
    S <= "01111110" after 15 ns, "01010101" after 32 ns,
         "10101010" after 51 ns;
    wait;
  end process;

  process(CLK)
  begin
    CLK <= not CLK after 10 ns;
  end process;
end LATCH_TEST;