use WORK.all;

entity TEST_BENCH is
end TEST_BENCH;

architecture FA_TEST of TEST_BENCH is
  signal RUN, CLK : BIT;
  signal PG: BIT_VECTOR(2 downto 0);
  signal Z: BIT_VECTOR(1 downto 0);

begin
  L1: entity full_adder(df)
    generic map(2 ns, 2 ns)
    port map(A => PG(2), B => PG(1), CI => PG(0), 
             SUM => Z(1), COUT => Z(0));
  L2 : entity pulse_gen(alg)
    generic map(3, 20 ns)
    port map(RUN, PG);

  process
  begin
    RUN <= '1', '0' after 10 ns;
    wait;
  end process;
end FA_TEST;