TimeQuest Timing Analyzer report for counter
Tue Feb 18 09:00:16 2020
Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Timing Closure Recommendations
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'CLK'
 13. Slow 1200mV 85C Model Hold: 'CLK'
 14. Slow 1200mV 85C Model Metastability Summary
 15. Slow 1200mV 0C Model Fmax Summary
 16. Slow 1200mV 0C Model Setup Summary
 17. Slow 1200mV 0C Model Hold Summary
 18. Slow 1200mV 0C Model Recovery Summary
 19. Slow 1200mV 0C Model Removal Summary
 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
 21. Slow 1200mV 0C Model Setup: 'CLK'
 22. Slow 1200mV 0C Model Hold: 'CLK'
 23. Slow 1200mV 0C Model Metastability Summary
 24. Fast 1200mV 0C Model Setup Summary
 25. Fast 1200mV 0C Model Hold Summary
 26. Fast 1200mV 0C Model Recovery Summary
 27. Fast 1200mV 0C Model Removal Summary
 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
 29. Fast 1200mV 0C Model Setup: 'CLK'
 30. Fast 1200mV 0C Model Hold: 'CLK'
 31. Fast 1200mV 0C Model Metastability Summary
 32. Multicorner Timing Analysis Summary
 33. Board Trace Model Assignments
 34. Input Transition Times
 35. Signal Integrity Metrics (Slow 1200mv 0c Model)
 36. Signal Integrity Metrics (Slow 1200mv 85c Model)
 37. Signal Integrity Metrics (Fast 1200mv 0c Model)
 38. Setup Transfers
 39. Hold Transfers
 40. Report TCCS
 41. Report RSKM
 42. Unconstrained Paths Summary
 43. Clock Status Summary
 44. Unconstrained Input Ports
 45. Unconstrained Output Ports
 46. Unconstrained Input Ports
 47. Unconstrained Output Ports
 48. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+-----------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                           ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition ;
; Timing Analyzer       ; TimeQuest                                           ;
; Revision Name         ; counter                                             ;
; Device Family         ; Cyclone IV GX                                       ;
; Device Name           ; EP4CGX15BF14C6                                      ;
; Timing Models         ; Final                                               ;
; Delay Model           ; Combined                                            ;
; Rise/Fall Delays      ; Enabled                                             ;
+-----------------------+-----------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 48     ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                          ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; CLK        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                        ;
+------------+-----------------+------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
+------------+-----------------+------------+---------------------------------------------------------------+
; 806.45 MHz ; 250.0 MHz       ; CLK        ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+-------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+-------+--------+--------------------+
; Clock ; Slack  ; End Point TNS      ;
+-------+--------+--------------------+
; CLK   ; -0.240 ; -0.574             ;
+-------+--------+--------------------+


+------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+-------+-------+--------------------+
; Clock ; Slack ; End Point TNS      ;
+-------+-------+--------------------+
; CLK   ; 0.342 ; 0.000              ;
+-------+-------+--------------------+


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+---------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-------+--------+----------------------------------+
; Clock ; Slack  ; End Point TNS                    ;
+-------+--------+----------------------------------+
; CLK   ; -3.000 ; -7.000                           ;
+-------+--------+----------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLK'                                                                       ;
+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; -0.240 ; CNT[1]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.064     ; 1.171      ;
; -0.115 ; CNT[0]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.064     ; 1.046      ;
; -0.113 ; CNT[0]~reg0 ; CNT[0]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.064     ; 1.044      ;
; -0.111 ; CNT[2]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.078     ; 1.028      ;
; -0.110 ; CNT[2]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.078     ; 1.027      ;
; -0.077 ; CNT[0]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.253      ; 1.325      ;
; -0.073 ; CNT[0]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.253      ; 1.321      ;
; 0.073  ; CNT[1]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.253      ; 1.175      ;
; 0.074  ; CNT[1]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.253      ; 1.174      ;
; 0.258  ; CNT[3]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.078     ; 0.659      ;
+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLK'                                                                       ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; 0.342 ; CNT[3]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.078      ; 0.577      ;
; 0.342 ; CNT[2]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.078      ; 0.577      ;
; 0.356 ; CNT[1]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.064      ; 0.577      ;
; 0.471 ; CNT[1]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.395      ; 1.023      ;
; 0.474 ; CNT[1]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.395      ; 1.026      ;
; 0.555 ; CNT[0]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.395      ; 1.107      ;
; 0.608 ; CNT[0]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.395      ; 1.160      ;
; 0.673 ; CNT[2]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.078      ; 0.908      ;
; 0.702 ; CNT[0]~reg0 ; CNT[0]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.064      ; 0.923      ;
; 0.703 ; CNT[0]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.064      ; 0.924      ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+


-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                         ;
+------------+-----------------+------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
+------------+-----------------+------------+---------------------------------------------------------------+
; 906.62 MHz ; 250.0 MHz       ; CLK        ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+-------+--------+-------------------+
; Clock ; Slack  ; End Point TNS     ;
+-------+--------+-------------------+
; CLK   ; -0.103 ; -0.103            ;
+-------+--------+-------------------+


+-----------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+-------+-------+-------------------+
; Clock ; Slack ; End Point TNS     ;
+-------+-------+-------------------+
; CLK   ; 0.298 ; 0.000             ;
+-------+-------+-------------------+


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+-------+--------+---------------------------------+
; Clock ; Slack  ; End Point TNS                   ;
+-------+--------+---------------------------------+
; CLK   ; -3.000 ; -7.000                          ;
+-------+--------+---------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLK'                                                                        ;
+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; -0.103 ; CNT[1]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.057     ; 1.041      ;
; -0.003 ; CNT[0]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.057     ; 0.941      ;
; 0.000  ; CNT[0]~reg0 ; CNT[0]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.057     ; 0.938      ;
; 0.005  ; CNT[2]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.069     ; 0.921      ;
; 0.008  ; CNT[2]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.069     ; 0.918      ;
; 0.044  ; CNT[0]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.233      ; 1.184      ;
; 0.048  ; CNT[0]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.233      ; 1.180      ;
; 0.175  ; CNT[1]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.233      ; 1.053      ;
; 0.176  ; CNT[1]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.233      ; 1.052      ;
; 0.343  ; CNT[3]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.069     ; 0.583      ;
+--------+-------------+-------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLK'                                                                        ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; 0.298 ; CNT[3]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.069      ; 0.511      ;
; 0.298 ; CNT[2]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.069      ; 0.511      ;
; 0.310 ; CNT[1]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.057      ; 0.511      ;
; 0.417 ; CNT[1]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.359      ; 0.920      ;
; 0.419 ; CNT[1]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.359      ; 0.922      ;
; 0.495 ; CNT[0]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.359      ; 0.998      ;
; 0.539 ; CNT[0]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.359      ; 1.042      ;
; 0.602 ; CNT[2]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.069      ; 0.815      ;
; 0.625 ; CNT[0]~reg0 ; CNT[0]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.057      ; 0.826      ;
; 0.627 ; CNT[0]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.057      ; 0.828      ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+


----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.


+------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+-------+-------+--------------------+
; Clock ; Slack ; End Point TNS      ;
+-------+-------+--------------------+
; CLK   ; 0.309 ; 0.000              ;
+-------+-------+--------------------+


+-----------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+-------+-------+-------------------+
; Clock ; Slack ; End Point TNS     ;
+-------+-------+-------------------+
; CLK   ; 0.179 ; 0.000             ;
+-------+-------+-------------------+


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+-------+--------+---------------------------------+
; Clock ; Slack  ; End Point TNS                   ;
+-------+--------+---------------------------------+
; CLK   ; -3.000 ; -7.144                          ;
+-------+--------+---------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLK'                                                                       ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; 0.309 ; CNT[1]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.037     ; 0.641      ;
; 0.373 ; CNT[0]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.037     ; 0.577      ;
; 0.376 ; CNT[0]~reg0 ; CNT[0]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.037     ; 0.574      ;
; 0.380 ; CNT[2]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.044     ; 0.563      ;
; 0.386 ; CNT[2]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.044     ; 0.557      ;
; 0.395 ; CNT[0]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.138      ; 0.730      ;
; 0.395 ; CNT[0]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.138      ; 0.730      ;
; 0.480 ; CNT[1]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.138      ; 0.645      ;
; 0.486 ; CNT[1]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 1.000        ; 0.138      ; 0.639      ;
; 0.584 ; CNT[3]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 1.000        ; -0.044     ; 0.359      ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLK'                                                                        ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; 0.179 ; CNT[3]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; CNT[2]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.044      ; 0.307      ;
; 0.186 ; CNT[1]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.037      ; 0.307      ;
; 0.246 ; CNT[1]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.219      ; 0.549      ;
; 0.249 ; CNT[1]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.219      ; 0.552      ;
; 0.296 ; CNT[0]~reg0 ; CNT[2]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.219      ; 0.599      ;
; 0.329 ; CNT[0]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.219      ; 0.632      ;
; 0.354 ; CNT[2]~reg0 ; CNT[3]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.044      ; 0.482      ;
; 0.367 ; CNT[0]~reg0 ; CNT[0]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.037      ; 0.488      ;
; 0.369 ; CNT[0]~reg0 ; CNT[1]~reg0 ; CLK          ; CLK         ; 0.000        ; 0.037      ; 0.490      ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+


----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                          ;
+------------------+--------+-------+----------+---------+---------------------+
; Clock            ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack ; -0.240 ; 0.179 ; N/A      ; N/A     ; -3.000              ;
;  CLK             ; -0.240 ; 0.179 ; N/A      ; N/A     ; -3.000              ;
; Design-wide TNS  ; -0.574 ; 0.0   ; 0.0      ; 0.0     ; -7.144              ;
;  CLK             ; -0.574 ; 0.000 ; N/A      ; N/A     ; -7.144              ;
+------------------+--------+-------+----------+---------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; CNT[0]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CNT[1]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CNT[2]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CNT[3]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_NCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-------------------------------------------------------------------+
; Input Transition Times                                            ;
+----------------+--------------+-----------------+-----------------+
; Pin            ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+----------------+--------------+-----------------+-----------------+
; CNT[0]         ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CNT[1]         ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CNT[2]         ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CNT[3]         ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; COUNT          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; RESET          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; LOAD           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; DATA_IN[0]     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; CLK            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; UP             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; DATA_IN[1]     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; DATA_IN[2]     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; DATA_IN[3]     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_ASDO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_NCSO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+----------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; CNT[0]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
; CNT[1]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
; CNT[2]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
; CNT[3]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 4.76e-09 V                   ; 2.4 V               ; -0.034 V            ; 0.102 V                              ; 0.065 V                              ; 2.49e-10 s                  ; 3.49e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 4.76e-09 V                  ; 2.4 V              ; -0.034 V           ; 0.102 V                             ; 0.065 V                             ; 2.49e-10 s                 ; 3.49e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.0345 V           ; 0.156 V                              ; 0.089 V                              ; 2.68e-10 s                  ; 2.6e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.0345 V          ; 0.156 V                             ; 0.089 V                             ; 2.68e-10 s                 ; 2.6e-10 s                  ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; CNT[0]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
; CNT[1]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
; CNT[2]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
; CNT[3]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.93e-07 V                   ; 2.37 V              ; -0.0278 V           ; 0.106 V                              ; 0.115 V                              ; 2.69e-10 s                  ; 4.05e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.93e-07 V                  ; 2.37 V             ; -0.0278 V          ; 0.106 V                             ; 0.115 V                             ; 2.69e-10 s                 ; 4.05e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.76e-07 V                   ; 2.36 V              ; -0.00505 V          ; 0.088 V                              ; 0.006 V                              ; 4.05e-10 s                  ; 3.35e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.76e-07 V                  ; 2.36 V             ; -0.00505 V         ; 0.088 V                             ; 0.006 V                             ; 4.05e-10 s                 ; 3.35e-10 s                 ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; CNT[0]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
; CNT[1]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
; CNT[2]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
; CNT[3]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.06e-08 V                   ; 2.86 V              ; -0.0341 V           ; 0.364 V                              ; 0.046 V                              ; 1.17e-10 s                  ; 2.6e-10 s                   ; No                         ; Yes                        ; 2.62 V                      ; 3.06e-08 V                  ; 2.86 V             ; -0.0341 V          ; 0.364 V                             ; 0.046 V                             ; 1.17e-10 s                 ; 2.6e-10 s                  ; No                        ; Yes                       ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.81e-08 V                   ; 2.72 V              ; -0.0548 V           ; 0.144 V                              ; 0.087 V                              ; 2.55e-10 s                  ; 2.14e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 3.81e-08 V                  ; 2.72 V             ; -0.0548 V          ; 0.144 V                             ; 0.087 V                             ; 2.55e-10 s                 ; 2.14e-10 s                 ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------+
; Setup Transfers                                                   ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; CLK        ; CLK      ; 12       ; 0        ; 0        ; 0        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------+
; Hold Transfers                                                    ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; CLK        ; CLK      ; 12       ; 0        ; 0        ; 0        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths Summary                    ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 8     ; 8    ;
; Unconstrained Input Port Paths  ; 19    ; 19   ;
; Unconstrained Output Ports      ; 4     ; 4    ;
; Unconstrained Output Port Paths ; 4     ; 4    ;
+---------------------------------+-------+------+


+-------------------------------------+
; Clock Status Summary                ;
+--------+-------+------+-------------+
; Target ; Clock ; Type ; Status      ;
+--------+-------+------+-------------+
; CLK    ; CLK   ; Base ; Constrained ;
+--------+-------+------+-------------+


+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports                                                                         ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment                                                                              ;
+------------+--------------------------------------------------------------------------------------+
; COUNT      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DATA_IN[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DATA_IN[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DATA_IN[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DATA_IN[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; LOAD       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RESET      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; UP         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                          ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment                                                                               ;
+-------------+---------------------------------------------------------------------------------------+
; CNT[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CNT[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CNT[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CNT[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports                                                                         ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment                                                                              ;
+------------+--------------------------------------------------------------------------------------+
; COUNT      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DATA_IN[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DATA_IN[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DATA_IN[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DATA_IN[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; LOAD       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RESET      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; UP         ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                          ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment                                                                               ;
+-------------+---------------------------------------------------------------------------------------+
; CNT[0]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CNT[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CNT[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CNT[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Feb 18 09:00:14 2020
Info: Command: quartus_sta counter -c counter
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name CLK CLK
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -0.240
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.240              -0.574 CLK 
Info (332146): Worst-case hold slack is 0.342
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.342               0.000 CLK 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000              -7.000 CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -0.103
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.103              -0.103 CLK 
Info (332146): Worst-case hold slack is 0.298
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.298               0.000 CLK 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000              -7.000 CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 0.309
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.309               0.000 CLK 
Info (332146): Worst-case hold slack is 0.179
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.179               0.000 CLK 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000              -7.144 CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Peak virtual memory: 1161 megabytes
    Info: Processing ended: Tue Feb 18 09:00:16 2020
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


