use WORK.all;
library ieee;
use ieee.std_logic_1164.all;

entity TEST_BENCH is
end TEST_BENCH;

architecture COUNTER_TEST of TEST_BENCH is
  signal CLK : std_logic := '0';
  signal RUN : bit;
  signal PG : std_logic_VECTOR(3 downto 0);
  signal S0 : std_logic_VECTOR(3 downto 0) := "0000";
  signal S1 : std_logic_VECTOR(3 downto 0) := "0101";
  signal S2 : bit_VECTOR(3 downto 0) := "1010";
  signal S3 : std_logic_VECTOR(3 downto 0) := "1111";
  signal Z : std_logic_VECTOR(3 downto 0);

begin
  L1: entity counter(structure)
    --generic map(2 ns)
    port map(RESET => PG(3), LOAD => PG(2), COUNT => PG(1),
             UP => PG(0), CLK => CLK, DATA_IN => S2, CNT => Z);

  L2 : entity pulse_gen(alg)
    generic map(4, 800 ns)
    port map(RUN, PG);

  process
  begin
    RUN <= '1', '0' after 10 ns;
    wait;
  end process;

  process(CLK)
  begin
    CLK <= not CLK after 10 ns;
  end process;
end COUNTER_TEST;