use WORK.all;
entity TEST_BENCH is
end TEST_BENCH;

architecture ALU_TEST of TEST_BENCH is
  signal RUN, CLK : BIT;
  signal PG : BIT_VECTOR(10 downto 0);
  signal S0 : BIT_VECTOR(3 downto 0) := "0000";
  signal S1 : BIT_VECTOR(3 downto 0) := "1101";
  signal S2 : BIT_VECTOR(3 downto 0) := "1010";
  signal S3 : BIT_VECTOR(3 downto 0) := "1111";
  signal Z : BIT_VECTOR(4 downto 0);

begin
  L1: entity alu(alg)
    generic map(2 ns)
    port map(A => PG(7 downto 4), B => PG(3 downto 0), 
             CI => PG(10), FSEL(1) => PG(9),
             FSEL(0) => PG(8), COUT => Z(4),
             F(3 downto 0) => Z(3 downto 0));
  L2 : entity pulse_gen(alg)
    generic map(11, 20 ns)
    port map(RUN, PG);

  process
  begin
    RUN <= '1', '0' after 10 ns;
    wait;
  end process;
end ALU_TEST;