library ieee;
use ieee.std_logic_1164.all;

entity TWO_TO_4_DEC is
  generic(DEL: TIME);
  port(I: in  std_logic_vector(1 downto 0);
       EN : in std_logic;
       O: out std_logic_vector(3 downto 0));
end TWO_TO_4_DEC;

architecture ALG of TWO_TO_4_DEC is
  signal O_INT : std_logic_vector(3 downto 0);
begin
   --O_INT <= "0001" after DEL when I = "00" else
    --        "0010" after DEL when I = "01" else
    --        "0100" after DEL when I = "10" else
    --        "1000" after DEL when I = "11" else
    --         O_INT;
   O <= "ZZZZ" when EN = '0' else
        O_INT when EN = '1';
  process(I, EN)
    variable TEMP : std_logic_vector(2 downto 0) := I & EN;
  begin
    with TEMP select
      O_INT <= "0001" after DEL when "001",
              "0010" after DEL when "011",
              "0100" after DEL when "101",
              "1000" after DEL when "111",
              "ZZZZ" after DEL when "--0",
               O_INT after DEL when others;
  end process;,
end ALG;