entity prob is
  port (D : out bit);
end prob;

architecture PROB of PROB is
  signal A, B, C, E, F : bit;
begin
  process
  begin
    A <= '1' after 5 ns;
    wait;
  end process;
  P1: process (F, C)
  begin
    B <= F after 4 ns;
    E <= C after 6 ns;
  end process P1;
  C <= transport A or B 
         after 3 ns;
  P2: process (C, E)
  begin
    F <= (C xor E) after 4 ns;
  end process P2;
  D <= F xor (B and C) after 2 ns;
end PROB;