library ieee;
use ieee.std_logic_1164.all;

package needit is
  function pre_app(vect : in std_logic_vector;
                   sub : in std_logic_vector;
                   ins_pos : in natural) return std_logic_vector;
end needit;

package body needit is
  function pre_app(vect : in std_logic_vector; 
                   sub : in std_logic_vector;
                   ins_pos : in natural)
    return std_logic_vector is
    variable result : std_logic_vector(vect'length + sub'length - 1 downto 0);
  begin
    if (ins_pos = 0) then
      result := vect & sub;
    elsif (ins_pos = 1) then
      result := sub & vect;
    else
      report "invalid value of ins_pos";
    end if;
    return result;
  end pre_app;
end package body needit;

use work.needit.all;
library ieee;
use ieee.std_logic_1164.all;

entity test_pre_app is
end test_pre_app;

architecture mine of test_pre_app is
begin
  process
    variable a : std_logic_vector(10 downto 0) := "00000011100";
    variable b : std_logic_vector(3 downto 0):= "0010";
    variable c : std_logic_vector(14 downto 0);
  begin
    c := pre_app(a, b, 0);
    wait for 10 ns;
    c := pre_app(a, b, 1);
    wait for 10 ns;
    c := pre_app(a, b, 2);
    wait;
  end process;
end mine;