library ieee;
use ieee.std_logic_1164.all;

entity DLATCH is 
  generic (TPDQ, TPCQ, TPRQ : time);
  port (d, clk, r : in std_logic;
        q, qb : out std_logic);
end entity DLATCH;

architecture DLATCH of DLATCH is
   signal q_temp : std_logic;
begin
  process(d, clk, r)
  begin
    if (r = '0' and r'event) then
       q_temp <= '0' after TPRQ;
    elsif (clk = '1' and d'event) then
      q_temp <= d after TPDQ;
    elsif (clk = '1' and clk'event) then
      q_temp <= d after TPCQ;
    end if;
  end process;
    q <= q_temp;
    qb <= not q_temp;
end DLATCH;