library ieee;
use ieee.std_logic_1164.all;

entity barrel is
  port (a : in std_logic_vector(3 downto 0);
        s1, s0 : in std_logic;
        c : out std_logic_vector(3 downto 0));
end entity barrel;

architecture synth of barrel is
  --signal control : std_logic_vector(1 downto 0);
begin
  --control <= s1 & s0;
  with std_logic_vector'(s1, s1) select
    c <= a when "00",
         a(0) & a(3 downto 1) when "01",
         a(1 downto 0) & a(3 downto 2) when "10",
         a(2 downto 0) & a(3) when "11",
         a when others;
end synth;