library ieee;
use ieee.std_logic_1164.all;

entity ALU is
  generic(DEL: TIME);
  port(A,B: in std_logic_vector(3 downto 0); CI: in std_logic;
       FSEL: in std_logic_vector(1 downto 0);
       F: out std_logic_vector(3 downto 0); COUT: out std_logic);
end ALU;


library ieee;
use ieee.std_logic_1164.all;

entity ALU8 is
  generic (DEL : TIME);
  port (A, B : in std_logic_vector(7 downto 0);
        CI : in std_logic;
        FSEL : in std_logic_vector(1 downto 0);
        F : out std_logic_vector(7 downto 0);
        COUT : out std_logic);
end ALU8;

architecture ALU8 of ALU8 is
  component ALU is
    generic (DEL : TIME);
    port (A, B : in std_logic_vector(3 downto 0);
        CI : in std_logic;
        FSEL : in std_logic_vector(1 downto 0);
        F : out std_logic_vector(3 downto 0);
        COUT : out std_logic);
  end component ALU;
  signal TEMP : std_logic;
begin
  U0 : ALU generic map (DEL)
                       port map (A => A(3 downto 0),
                                 B => B(3 downto 0),
                                 CI => CI, FSEL => FSEL,
                                 F => F(3 downto 0),
                                 COUT => TEMP);
  U1 : ALU generic map (DEL)
                       port map (A => A(7 downto 4),
                                 B => B(7 downto 4),
                                 CI => TEMP, FSEL => FSEL,
                                 F => F(7 downto 4),
                                 COUT => COUT);
end ALU8;