library ieee;
use ieee.std_logic_1164.all;

entity RACE is
  port (CLK, S, RESET  : in std_logic;
        R, Y, G : out std_logic);
end RACE;

architecture SYNTH of RACE is
  type STATE_TYPE is (Reset_State, Stay_Red, Yellow, First_Green, 
                      Second_Green, Third_Green);
  signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
  process(CLK, RESET)
  begin
    if (RESET = '1') then
      CURRENT_STATE <= Reset_State;
    elsif (CLK'event and CLK = '1') then
      CURRENT_STATE <= NEXT_STATE;
    end if;
  end process;
  process(S, CURRENT_STATE)
  begin
    case CURRENT_STATE is
      when Reset_State => if (S = '1') then
                            NEXT_STATE <= Stay_Red;
                          else
                            NEXT_STATE <= Reset_State;
                          end if;
      when Stay_Red => NEXT_STATE <= Yellow;
      when Yellow => NEXT_STATE <= First_Green;
      when First_Green => NEXT_STATE <= Second_Green;
      when Second_Green => NEXT_STATE <= Third_Green;
      when Third_Green => NEXT_STATE <= Reset_State;
    end case;
  end process;
  process (CURRENT_STATE)
  begin
    R <= '0'; Y <= '0'; G <= '0';
    case CURRENT_STATE is
      when Reset_State | Stay_Red => R <= '1'; 
      when Yellow => Y <= '1'; 
      when First_Green to Third_Green => G <= '1'; 
    end case;
  end process;
end SYNTH;