library ieee;
use ieee.std_logic_1164.all;

entity en_dec_328 is
  port (a : in std_logic_vector (2 downto 0);
        en : std_logic;
        d : out std_logic_vector (7 downto 0));
end entity en_dec_328;

architecture problem14 of en_dec_328 is
begin
    process (en, a)
    begin
        if (en = '1') then
            d <= "00000000";
        elsif (en = '0') then
            case (a) is
                when "000" => d <= "00000001";
                when "001" => d <= "00000010";
                when "010" => d <= "00000100";
                when "011" => d <= "00001000";
                when "100" => d <= "00010000";
                when "101" => d <= "00100000";
                when "110" => d <= "01000000";
                when "111" => d <= "10000000";
                when others => d <= "00000000";
            end case;
        end if;
    end process;
end architecture problem14;

library ieee;
use ieee.std_logic_1164.all;

entity en_dec_4216 is
    port(a : in std_logic_vector (3 downto 0);
         en : in std_logic;
         d : out std_logic_vector (15 downto 0));
end entity en_dec_4216;

architecture problem14b_c of en_dec_4216 is
    signal a_not : std_logic;
begin
    a_not <= '1' when a(3)='0' else
             '0' when a(3)='1';

    U0 : entity work.en_dec_328 port map (a => a (2 downto 0),
                                          en => a(3),
                                          d => d(7 downto 0));
                                          
    U1 : entity work.en_dec_328 port map (a => a (2 downto 0),
                                          en => a_not,
                                          d => d(15 downto 8));

end architecture problem14b_c;