library ieee;
use ieee.std_logic_1164.all;

entity t_ff is
  port (t, clk, r : in std_logic;
        q, qb : out std_logic);
end entity;

architecture synth of t_ff is
begin
  process (clk)
  begin
    if (clk'event and clk = '0') then
      if r = '1' then
        q <= '0';
        qb <= '1';
      elsif (t = '1') then
        q <= not q;
        qb <= not qb;
      end if;
    end if;
  end process;
end synth;