library ieee;
use ieee.std_logic_1164.all;

entity priority is
  port (i : in std_logic_vector (0 to 7);
        avalid, mul : out std_logic;
        a : out std_logic_vector (2 downto 0));
end entity priority;

architecture behave of priority is

begin
  process (i)
    variable count : integer;
  begin
    count := 0;
    for j in i'range loop
      if (i(j) = '0') then
        count := count + 1;
      end if;
    end loop;
    if count > 1 then
      mul <= '1'; avalid <= '1';
    elsif count = 1 then
      avalid <= '1'; mul <= '0';
    else
      mul <= '0'; avalid <= '0';
    end if;
    if (i(0) = '0') then a <= "000";
    elsif (i(1) = '0') then a <= "001";
    elsif (i(2) = '0') then a <= "010";
    elsif (i(3) = '0') then a <= "011";
    elsif (i(4) = '0') then a <= "100";
    elsif (i(5) = '0') then a <= "101";
    elsif (i(6) = '0') then a <= "110";
    elsif (i(7) = '0') then a <= "111";
    else  a <= "XXX";   
    end if;
  end process;
end behave;