TimeQuest Timing Analyzer report for tff
Sun Mar  5 15:43:23 2017
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Timing Closure Recommendations
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'clk'
 13. Slow 1200mV 85C Model Hold: 'clk'
 14. Slow 1200mV 85C Model Minimum Pulse Width: 'clk'
 15. Setup Times
 16. Hold Times
 17. Clock to Output Times
 18. Minimum Clock to Output Times
 19. Slow 1200mV 85C Model Metastability Report
 20. Slow 1200mV 0C Model Fmax Summary
 21. Slow 1200mV 0C Model Setup Summary
 22. Slow 1200mV 0C Model Hold Summary
 23. Slow 1200mV 0C Model Recovery Summary
 24. Slow 1200mV 0C Model Removal Summary
 25. Slow 1200mV 0C Model Minimum Pulse Width Summary
 26. Slow 1200mV 0C Model Setup: 'clk'
 27. Slow 1200mV 0C Model Hold: 'clk'
 28. Slow 1200mV 0C Model Minimum Pulse Width: 'clk'
 29. Setup Times
 30. Hold Times
 31. Clock to Output Times
 32. Minimum Clock to Output Times
 33. Slow 1200mV 0C Model Metastability Report
 34. Fast 1200mV 0C Model Setup Summary
 35. Fast 1200mV 0C Model Hold Summary
 36. Fast 1200mV 0C Model Recovery Summary
 37. Fast 1200mV 0C Model Removal Summary
 38. Fast 1200mV 0C Model Minimum Pulse Width Summary
 39. Fast 1200mV 0C Model Setup: 'clk'
 40. Fast 1200mV 0C Model Hold: 'clk'
 41. Fast 1200mV 0C Model Minimum Pulse Width: 'clk'
 42. Setup Times
 43. Hold Times
 44. Clock to Output Times
 45. Minimum Clock to Output Times
 46. Fast 1200mV 0C Model Metastability Report
 47. Multicorner Timing Analysis Summary
 48. Setup Times
 49. Hold Times
 50. Clock to Output Times
 51. Minimum Clock to Output Times
 52. Board Trace Model Assignments
 53. Input Transition Times
 54. Signal Integrity Metrics (Slow 1200mv 0c Model)
 55. Signal Integrity Metrics (Slow 1200mv 85c Model)
 56. Signal Integrity Metrics (Fast 1200mv 0c Model)
 57. Setup Transfers
 58. Hold Transfers
 59. Report TCCS
 60. Report RSKM
 61. Unconstrained Paths
 62. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                        ;
+--------------------+-----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name      ; tff                                                 ;
; Device Family      ; Cyclone IV GX                                       ;
; Device Name        ; EP4CGX15BF14C6                                      ;
; Timing Models      ; Final                                               ;
; Delay Model        ; Combined                                            ;
; Rise/Fall Delays   ; Enabled                                             ;
+--------------------+-----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 16          ;
; Maximum allowed            ; 8           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 8           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-8         ; < 0.1%      ;
;     Processors 9-16        ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                          ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; clk        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+


+------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                         ;
+-------------+-----------------+------------+---------------------------------------------------------------+
; Fmax        ; Restricted Fmax ; Clock Name ; Note                                                          ;
+-------------+-----------------+------------+---------------------------------------------------------------+
; 1373.63 MHz ; 250.0 MHz       ; clk        ; limit due to minimum period restriction (max I/O toggle rate) ;
+-------------+-----------------+------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+-------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+-------+-------+---------------------+
; Clock ; Slack ; End Point TNS       ;
+-------+-------+---------------------+
; clk   ; 0.272 ; 0.000               ;
+-------+-------+---------------------+


+------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+-------+-------+--------------------+
; Clock ; Slack ; End Point TNS      ;
+-------+-------+--------------------+
; clk   ; 0.359 ; 0.000              ;
+-------+-------+--------------------+


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+---------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-------+--------+----------------------------------+
; Clock ; Slack  ; End Point TNS                    ;
+-------+--------+----------------------------------+
; clk   ; -3.000 ; -5.000                           ;
+-------+--------+----------------------------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'clk'                                                                ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; 0.272 ; qb~reg0   ; qb~reg0 ; clk          ; clk         ; 1.000        ; -0.064     ; 0.659      ;
; 0.272 ; q~reg0    ; q~reg0  ; clk          ; clk         ; 1.000        ; -0.064     ; 0.659      ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'clk'                                                                 ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; 0.359 ; qb~reg0   ; qb~reg0 ; clk          ; clk         ; 0.000        ; 0.064      ; 0.580      ;
; 0.359 ; q~reg0    ; q~reg0  ; clk          ; clk         ; 0.000        ; 0.064      ; 0.580      ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'clk'                                                           ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Fall       ; qb~reg0                   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Fall       ; q~reg0                    ;
; 0.164  ; 0.380        ; 0.216          ; High Pulse Width ; clk   ; Fall       ; qb~reg0                   ;
; 0.164  ; 0.380        ; 0.216          ; High Pulse Width ; clk   ; Fall       ; q~reg0                    ;
; 0.326  ; 0.326        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o               ;
; 0.337  ; 0.337        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|inclk[0] ;
; 0.337  ; 0.337        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|outclk   ;
; 0.374  ; 0.374        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; qb~reg0|clk               ;
; 0.374  ; 0.374        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; q~reg0|clk                ;
; 0.430  ; 0.614        ; 0.184          ; Low Pulse Width  ; clk   ; Fall       ; qb~reg0                   ;
; 0.430  ; 0.614        ; 0.184          ; Low Pulse Width  ; clk   ; Fall       ; q~reg0                    ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i               ;
; 0.623  ; 0.623        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; qb~reg0|clk               ;
; 0.623  ; 0.623        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; q~reg0|clk                ;
; 0.662  ; 0.662        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|inclk[0] ;
; 0.662  ; 0.662        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|outclk   ;
; 0.674  ; 0.674        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|o               ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------+


+-----------------------------------------------------------------------+
; Setup Times                                                           ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; r         ; clk        ; 2.151 ; 2.565 ; Fall       ; clk             ;
; t         ; clk        ; 2.233 ; 2.667 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------+
; Hold Times                                                              ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; r         ; clk        ; -1.029 ; -1.433 ; Fall       ; clk             ;
; t         ; clk        ; -1.938 ; -2.359 ; Fall       ; clk             ;
+-----------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 5.815 ; 5.733 ; Fall       ; clk             ;
; qb        ; clk        ; 5.833 ; 5.751 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 5.638 ; 5.555 ; Fall       ; clk             ;
; qb        ; clk        ; 5.655 ; 5.573 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                         ;
+------------+-----------------+------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
+------------+-----------------+------------+---------------------------------------------------------------+
; 1552.8 MHz ; 250.0 MHz       ; clk        ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+-------+-------+--------------------+
; Clock ; Slack ; End Point TNS      ;
+-------+-------+--------------------+
; clk   ; 0.356 ; 0.000              ;
+-------+-------+--------------------+


+-----------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+-------+-------+-------------------+
; Clock ; Slack ; End Point TNS     ;
+-------+-------+-------------------+
; clk   ; 0.319 ; 0.000             ;
+-------+-------+-------------------+


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+-------+--------+---------------------------------+
; Clock ; Slack  ; End Point TNS                   ;
+-------+--------+---------------------------------+
; clk   ; -3.000 ; -5.000                          ;
+-------+--------+---------------------------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'clk'                                                                 ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; 0.356 ; qb~reg0   ; qb~reg0 ; clk          ; clk         ; 1.000        ; -0.056     ; 0.583      ;
; 0.356 ; q~reg0    ; q~reg0  ; clk          ; clk         ; 1.000        ; -0.056     ; 0.583      ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'clk'                                                                  ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; 0.319 ; qb~reg0   ; qb~reg0 ; clk          ; clk         ; 0.000        ; 0.056      ; 0.519      ;
; 0.319 ; q~reg0    ; q~reg0  ; clk          ; clk         ; 0.000        ; 0.056      ; 0.519      ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'clk'                                                            ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Fall       ; qb~reg0                   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Fall       ; q~reg0                    ;
; 0.175  ; 0.391        ; 0.216          ; High Pulse Width ; clk   ; Fall       ; qb~reg0                   ;
; 0.175  ; 0.391        ; 0.216          ; High Pulse Width ; clk   ; Fall       ; q~reg0                    ;
; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o               ;
; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|inclk[0] ;
; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|outclk   ;
; 0.377  ; 0.377        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; qb~reg0|clk               ;
; 0.377  ; 0.377        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; q~reg0|clk                ;
; 0.422  ; 0.606        ; 0.184          ; Low Pulse Width  ; clk   ; Fall       ; qb~reg0                   ;
; 0.422  ; 0.606        ; 0.184          ; Low Pulse Width  ; clk   ; Fall       ; q~reg0                    ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i               ;
; 0.621  ; 0.621        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; qb~reg0|clk               ;
; 0.621  ; 0.621        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; q~reg0|clk                ;
; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|inclk[0] ;
; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|outclk   ;
; 0.656  ; 0.656        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|o               ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------+


+-----------------------------------------------------------------------+
; Setup Times                                                           ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; r         ; clk        ; 1.840 ; 2.179 ; Fall       ; clk             ;
; t         ; clk        ; 1.913 ; 2.273 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------+
; Hold Times                                                              ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; r         ; clk        ; -0.823 ; -1.159 ; Fall       ; clk             ;
; t         ; clk        ; -1.651 ; -2.002 ; Fall       ; clk             ;
+-----------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 5.219 ; 5.111 ; Fall       ; clk             ;
; qb        ; clk        ; 5.236 ; 5.127 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 5.059 ; 4.950 ; Fall       ; clk             ;
; qb        ; clk        ; 5.075 ; 4.966 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+-------+-------+--------------------+
; Clock ; Slack ; End Point TNS      ;
+-------+-------+--------------------+
; clk   ; 0.589 ; 0.000              ;
+-------+-------+--------------------+


+-----------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+-------+-------+-------------------+
; Clock ; Slack ; End Point TNS     ;
+-------+-------+-------------------+
; clk   ; 0.191 ; 0.000             ;
+-------+-------+-------------------+


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+-------+--------+---------------------------------+
; Clock ; Slack  ; End Point TNS                   ;
+-------+--------+---------------------------------+
; clk   ; -3.000 ; -5.138                          ;
+-------+--------+---------------------------------+


+---------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'clk'                                                                 ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; 0.589 ; qb~reg0   ; qb~reg0 ; clk          ; clk         ; 1.000        ; -0.039     ; 0.359      ;
; 0.589 ; q~reg0    ; q~reg0  ; clk          ; clk         ; 1.000        ; -0.039     ; 0.359      ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'clk'                                                                  ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+
; 0.191 ; qb~reg0   ; qb~reg0 ; clk          ; clk         ; 0.000        ; 0.039      ; 0.314      ;
; 0.191 ; q~reg0    ; q~reg0  ; clk          ; clk         ; 0.000        ; 0.039      ; 0.314      ;
+-------+-----------+---------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'clk'                                                            ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------+
; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                       ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Fall       ; qb~reg0                   ;
; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Fall       ; q~reg0                    ;
; -0.069 ; 0.147        ; 0.216          ; High Pulse Width ; clk   ; Fall       ; qb~reg0                   ;
; -0.069 ; 0.147        ; 0.216          ; High Pulse Width ; clk   ; Fall       ; q~reg0                    ;
; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o               ;
; 0.139  ; 0.139        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|inclk[0] ;
; 0.139  ; 0.139        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|outclk   ;
; 0.153  ; 0.153        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; qb~reg0|clk               ;
; 0.153  ; 0.153        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; q~reg0|clk                ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i               ;
; 0.668  ; 0.852        ; 0.184          ; Low Pulse Width  ; clk   ; Fall       ; qb~reg0                   ;
; 0.668  ; 0.852        ; 0.184          ; Low Pulse Width  ; clk   ; Fall       ; q~reg0                    ;
; 0.847  ; 0.847        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; qb~reg0|clk               ;
; 0.847  ; 0.847        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; q~reg0|clk                ;
; 0.861  ; 0.861        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|inclk[0] ;
; 0.861  ; 0.861        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|outclk   ;
; 0.875  ; 0.875        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|o               ;
+--------+--------------+----------------+------------------+-------+------------+---------------------------+


+-----------------------------------------------------------------------+
; Setup Times                                                           ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; r         ; clk        ; 0.905 ; 1.469 ; Fall       ; clk             ;
; t         ; clk        ; 0.945 ; 1.518 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------+
; Hold Times                                                              ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; r         ; clk        ; -0.285 ; -0.835 ; Fall       ; clk             ;
; t         ; clk        ; -0.773 ; -1.338 ; Fall       ; clk             ;
+-----------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 3.679 ; 3.706 ; Fall       ; clk             ;
; qb        ; clk        ; 3.692 ; 3.720 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 3.570 ; 3.595 ; Fall       ; clk             ;
; qb        ; clk        ; 3.583 ; 3.609 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                         ;
+------------------+-------+-------+----------+---------+---------------------+
; Clock            ; Setup ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+-------+----------+---------+---------------------+
; Worst-case Slack ; 0.272 ; 0.191 ; N/A      ; N/A     ; -3.000              ;
;  clk             ; 0.272 ; 0.191 ; N/A      ; N/A     ; -3.000              ;
; Design-wide TNS  ; 0.0   ; 0.0   ; 0.0      ; 0.0     ; -5.138              ;
;  clk             ; 0.000 ; 0.000 ; N/A      ; N/A     ; -5.138              ;
+------------------+-------+-------+----------+---------+---------------------+


+-----------------------------------------------------------------------+
; Setup Times                                                           ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; r         ; clk        ; 2.151 ; 2.565 ; Fall       ; clk             ;
; t         ; clk        ; 2.233 ; 2.667 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------+
; Hold Times                                                              ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; r         ; clk        ; -0.285 ; -0.835 ; Fall       ; clk             ;
; t         ; clk        ; -0.773 ; -1.338 ; Fall       ; clk             ;
+-----------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 5.815 ; 5.733 ; Fall       ; clk             ;
; qb        ; clk        ; 5.833 ; 5.751 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; q         ; clk        ; 3.570 ; 3.595 ; Fall       ; clk             ;
; qb        ; clk        ; 3.583 ; 3.609 ; Fall       ; clk             ;
+-----------+------------+-------+-------+------------+-----------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; q             ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; qb            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_NCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-------------------------------------------------------------------+
; Input Transition Times                                            ;
+----------------+--------------+-----------------+-----------------+
; Pin            ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+----------------+--------------+-----------------+-----------------+
; r              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; clk            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; t              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_ASDO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_NCSO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+----------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; q             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
; qb            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 4.76e-09 V                   ; 2.4 V               ; -0.034 V            ; 0.102 V                              ; 0.065 V                              ; 2.49e-10 s                  ; 3.49e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 4.76e-09 V                  ; 2.4 V              ; -0.034 V           ; 0.102 V                             ; 0.065 V                             ; 2.49e-10 s                 ; 3.49e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.94e-09 V                   ; 2.39 V              ; -0.0343 V           ; 0.156 V                              ; 0.09 V                               ; 2.68e-10 s                  ; 2.6e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.94e-09 V                  ; 2.39 V             ; -0.0343 V          ; 0.156 V                             ; 0.09 V                              ; 2.68e-10 s                 ; 2.6e-10 s                  ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; q             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
; qb            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.93e-07 V                   ; 2.37 V              ; -0.0278 V           ; 0.106 V                              ; 0.115 V                              ; 2.69e-10 s                  ; 4.05e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.93e-07 V                  ; 2.37 V             ; -0.0278 V          ; 0.106 V                             ; 0.115 V                             ; 2.69e-10 s                 ; 4.05e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.76e-07 V                   ; 2.36 V              ; -0.00433 V          ; 0.088 V                              ; 0.007 V                              ; 4.05e-10 s                  ; 3.35e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.76e-07 V                  ; 2.36 V             ; -0.00433 V         ; 0.088 V                             ; 0.007 V                             ; 4.05e-10 s                 ; 3.35e-10 s                 ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; q             ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
; qb            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.06e-08 V                   ; 2.86 V              ; -0.0341 V           ; 0.364 V                              ; 0.046 V                              ; 1.17e-10 s                  ; 2.6e-10 s                   ; No                         ; Yes                        ; 2.62 V                      ; 3.06e-08 V                  ; 2.86 V             ; -0.0341 V          ; 0.364 V                             ; 0.046 V                             ; 1.17e-10 s                 ; 2.6e-10 s                  ; No                        ; Yes                       ;
; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.81e-08 V                   ; 2.72 V              ; -0.0546 V           ; 0.144 V                              ; 0.087 V                              ; 2.55e-10 s                  ; 2.14e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 3.81e-08 V                  ; 2.72 V             ; -0.0546 V          ; 0.144 V                             ; 0.087 V                             ; 2.55e-10 s                 ; 2.14e-10 s                 ; Yes                       ; Yes                       ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------+
; Setup Transfers                                                   ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk        ; clk      ; 0        ; 0        ; 0        ; 2        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------+
; Hold Transfers                                                    ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk        ; clk      ; 0        ; 0        ; 0        ; 2        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 2     ; 2    ;
; Unconstrained Input Port Paths  ; 4     ; 4    ;
; Unconstrained Output Ports      ; 2     ; 2    ;
; Unconstrained Output Port Paths ; 2     ; 2    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Info: Processing started: Sun Mar  5 15:43:20 2017
Info: Command: quartus_sta tff -c tff
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 16 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 8 of the 8 physical processors detected instead.
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'tff.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name clk clk
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332146): Worst-case setup slack is 0.272
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.272               0.000 clk 
Info (332146): Worst-case hold slack is 0.359
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.359               0.000 clk 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000              -5.000 clk 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 0.356
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.356               0.000 clk 
Info (332146): Worst-case hold slack is 0.319
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.319               0.000 clk 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000              -5.000 clk 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 0.589
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.589               0.000 clk 
Info (332146): Worst-case hold slack is 0.191
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.191               0.000 clk 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case minimum pulse width slack is -3.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.000              -5.138 clk 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 793 megabytes
    Info: Processing ended: Sun Mar  5 15:43:23 2017
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:03


