library ieee;
use ieee.std_logic_1164.all;
use work.all;

entity dec3to8 is
  port (x : in std_logic_vector (2 downto 0);
        en : in std_logic;
        y : out std_logic_vector (7 downto 0));
end entity dec3to8;

library ieee;
use ieee.std_logic_1164.all;
use work.all;

entity dec5to32 is
  port (x : in std_logic_vector (4 downto 0);
        en : in std_logic;
        y : out std_logic_vector (31 downto 0));
end entity dec5to32;

architecture structure of dec5to32 is
  signal temp : std_logic_vector (7 downto 0);
begin
  U0 : entity dec3to8
       port map (x(2) => '0', x(1) => x(4), x(0) => x(3), y => temp, en => en);
  U1 : entity dec3to8(behave)
       port map (x => x(2 downto 0), en => temp(3), y => y(31 downto 24));
  U2 : entity dec3to8(behave)
       port map (x => x(2 downto 0), en => temp(2), y => y(23 downto 16));
  U3 : entity dec3to8(behave)
       port map (x => x(2 downto 0), en => temp(1), y => y(15 downto 8));
  U4 : entity dec3to8(behave)
       port map (x => x(2 downto 0), en => temp(0), y => y(7 downto 0));
end structure;