entity PROB is
  port (D : inout bit);
end PROB;

architecture PROB of PROB is
  signal A, B, C, E, F : bit;
  signal G, H, I, J, K, L : bit;
begin
  G <= C'transaction;
  H <= A'transaction;
  I <= B'transaction;
  J <= D'transaction;
  K <= E'transaction;
  L <= F'transaction;
  STIMULI : process
  begin
    A <= '1' after 5 ns, '0' after 10 ns;
    wait;
  end process STIMULI;
  P1: process (A, C)
  begin
    B <= A after 2 ns;
    E <= transport C after 5 ns;
  end process P1;
  C1: C <= transport A and B after 6 ns;
  P2: process (C, E)
  begin
    F <= reject 3 ns inertial C and E after 5 ns;
  end process P2;
  C2: D <= A or B or C or F after 2 ns;
end PROB;