library ieee;
use ieee.std_logic_1164.all;
use work.all;

entity SHIFTER is
  port (CLRB : in std_logic;
        CLOCK : in std_logic;
        SEL : in std_logic_vector(2 downto 0);
        R, L : in std_logic;
        X : in std_logic_vector(7 downto 0);
        Y : out std_logic_vector(7 downto 0));
end SHIFTER;

architecture STRUCTURE of SHIFTER is
  signal TEMP0, TEMP1 : std_logic_vector(7 downto 0);
  signal t0, t1 : std_logic;
begin
  U1 : entity S74194 port map(CLRB => CLRB, CLK => CLOCK,
                       S1 => Sel(1), S0 => sel(0),
                       SDR => t0 , SDL => TEMP1(3),
                       D => TEMP0(7 downto 4),
                       Q => TEMP1(7 downto 4));
  U2 : entity S74194 port map(CLRB => CLRB, CLK => CLOCK,
                       S1 => sel(1), S0 => sel(0),
                       SDR => TEMP1(4), SDL => t1, 
                       D => TEMP0(3 downto 0),
                       Q => TEMP1(3 downto 0));
  t0 <= R when sel = "010" else TEMP1(0);
  t1 <= L when sel = "001" else TEMP1(7);
  TEMP0 <= "00000000" when sel = "111" else X;
  Y <= TEMP1;
end STRUCTURE;