library ieee;
use ieee.std_logic_1164.all;

entity roman is
  port (d : in std_logic_vector (3 downto 0);
        r : out std_logic_vector (7 downto 0));
end entity roman;

architecture behave of roman is
begin
  process (d)
  begin
    case d is
      when "0001" => r <= "00000001";
      when "0010" => r <= "00001001"; 
      when "0011" => r <= "00011001";  
      when "0100" => r <= "00011010";  
      when "0101" => r <= "00001010"; 
      when "0110" => r <= "10100001"; 
      when "0111" => r <= "10101001"; 
      when "1000" => r <= "10010110"; 
      when "1001" => r <= "00010110"; 
      when "1010" => r <= "00000110"; 
      when others => r <= X"dd";
    end case;
  end process;
end behave;