library ieee;
use ieee.std_logic_1164.all;

entity roman is
  port (d : in std_logic_vector (3 downto 0);
        r : out std_logic_vector (7 downto 0));
end entity roman;

architecture behave of roman is
begin
  r <= "00000001" when d = "0001" else
       "00001001" when d = "0010" else
       "00011001" when d = "0011" else
       "00011010" when d = "0100" else
       "00001010" when d = "0101" else
       "10100001" when d = "0110" else
       "10101001" when d = "0111" else
       "10010110" when d = "1000" else
       "00010110" when d = "1001" else
       "00000110" when d = "1010" else
       "00000000";
end behave;