library ieee;
use ieee.std_logic_1164.all;

entity OR_DEL is
  generic (TPLH, TPHL : time := 2 ns);
  port (x, y : in std_logic;
        f    : out std_logic);
end OR_DEL;

architecture OLD of OR_DEL is
begin
  process (x, y)
    variable current, old : std_logic;
  begin
    current := x or y;
    if (current = '1' and old /= '1') then
      f <= x or y after TPLH;
    elsif (current = '0' and old /= '0') then
      f <= x or y after TPHL;
    end if;
    old := current;
  end process;
end OLD;

architecture NO_OLD of OR_DEL is
begin
  process (x, y)
    variable current : std_logic;
  begin
    current := x or y;
    if (current = '1') then
      f <= x or y after TPLH;
    elsif (current = '0') then
      f <= x or y after TPHL;
    end if;
  end process;
end NO_OLD;

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture testbench of testbench is
  signal a, b : std_logic;
  signal f : std_logic_vector(1 downto 0);
begin
  DUT0 : entity work.OR_DEL(OLD)
          generic map (TPLH => 5 ns, TPHL => 3 ns)
          port map (x => a, y => b, f => f(0));

  DUT1 : entity work.OR_DEL(NO_OLD)
          generic map (TPLH => 5 ns, TPHL => 3 ns)
          port map (x => a, y => b, f => f(1));
  process
  begin
    a <= '0' after 3 ns, '1' after 5 ns, '0' after 10 ns,
         '1' after 14 ns, '0' after 20 ns, '1' after 27 ns,
         '0' after 35 ns, '1' after 42 ns, '0' after 44 ns;
    b <= '0' after 2 ns, '1' after 8 ns, '0' after 15 ns,
         '1' after 17 ns, '0' after 23 ns, '1' after 29 ns,
         '0' after 32 ns, '1' after 42 ns, '0' after 47 ns;
    wait;
  end process;
end testbench;