entity SR is
  port (S, R : in bit;
        Q : out bit);
end SR;

architecture CONDITIONAL of SR is
begin
  with bit_vector'(S, R) select
    Q <= unaffected when "00", 
         '0' when "01",
         '1' when "10" | "11";
end CONDITIONAL;

architecture SEQUENTIAL of SR is
begin
  process (S, R) 
  begin
    case bit_vector'(S, R) is
      when "01" => Q <= '0';
      when "10" | "11" => Q <= '1';
      when others => null;
    end case;
  end process;
end SEQUENTIAL;

architecture SEQUENTIAL2 of SR is
begin
  process (S, R) 
  begin
    if (s&r = "01") then
      Q <= '0';
    else
    end if;
  end process;
end SEQUENTIAL2;