library ieee;
use ieee.std_logic_1164.all;

entity DFF_SYNTH is
  port (D, C, S, R : in std_logic;
        Q, QB : out std_logic);
end DFF_SYNTH;

architecture SYNTH of DFF_SYNTH is
  signal TEMP : std_logic;
begin
  process (c)
  begin
    if (C'event and C = '1') then
      if (S = '1') then
        TEMP <= '1';
      elsif (R = '1') then
        TEMP <= '0';
      else
        TEMP <= D;
      end if;
    end if;
  end process;
  Q <= TEMP;
  QB <= not TEMP;
end SYNTH;