library ieee;
use ieee.std_logic_1164.all;
use WORK.all;

entity COUNTER_14 is
  port (D : in std_logic_vector (13 downto 0);
        CLK_N : in std_logic;
        LOAD_EN : in std_logic;
        RESET : in std_logic;
        Q : out std_logic_vector (13 downto 0));
end COUNTER_14;

architecture STRUCT of COUNTER_14 is
  signal TEMP : std_logic_vector (13 downto 0); 
  signal LOAD : std_logic;
  signal LOAD_DATA : std_logic_vector (13 downto 0);
  signal USELESS : std_logic_vector (1 downto 0);
begin
  C3 : entity COUNTER 
         port map (CLK_N => TEMP(11), LOAD_EN => LOAD, RESET => RESET,
                   Q(3 downto 2) => USELESS, Q(1 downto 0) => TEMP(13 downto 12),
                   D(3) => '0', D(2) => '0', D(1 downto 0) => LOAD_DATA(13 downto 12));
  C2 : entity COUNTER 
         port map (CLK_N => TEMP(7), LOAD_EN => LOAD, RESET => RESET,
                   Q => TEMP(11 downto 8), D => LOAD_DATA(11 downto 8)); 
  C1 : entity COUNTER 
         port map (CLK_N => TEMP(3), LOAD_EN => LOAD, RESET => RESET,
                   Q => TEMP(7 downto 4), D => LOAD_DATA(7 downto 4)); 
  C0 : entity COUNTER 
         port map (CLK_N => CLK_N, LOAD_EN => LOAD, RESET => RESET,
                   Q => TEMP(3 downto 0), D => LOAD_DATA(3 downto 0)); 
  LOAD <= '1' when RESET = '1' else
          '1' when TEMP(13 downto 0) = "11111111111111" else 
          LOAD_EN;
  LOAD_DATA <= "00000000000000" when RESET = '1' else
               "00000000000000" when TEMP(13 downto 0) = "11111111111111" else
               LOAD_DATA;
  Q <= TEMP;
end STRUCT;