library ieee;
use ieee.std_logic_1164.all;

entity NXOR is 
  generic (N : integer);
  port (INPUT : std_logic_vector (N-1 downto 0);
        OUTPUT : out std_logic);
end NXOR;

architecture BEHAV of NXOR is
begin
  process (INPUT)
    variable TEMP : std_logic;
  begin
    TEMP := '0';
    for I in N-1 downto 0 loop
      TEMP := TEMP xor INPUT(I);
    end loop;
    OUTPUT <= TEMP;
  end process;
end BEHAV;