interface AHB_IF (input bit CLK);
  logic HWRITE;
  logic [1:0] HTRANS;
  logic [7:0] HWDATA, HRDATA;
  logic [20:0] HADDR;

  clocking CB @(negedge CLK);
    input HRDATA;
    output HADDR, HWRITE, HTRANS, HWDATA;
  endclocking;
  always @(negedge AHBIF.CB)begin
      if (AHBIF.HTRANS != 2'b00  && AHBIF.HTRANS != 2'b10) 
        $display ("Error : Wrong transaction type");
  end
 
  modport slave(input CLK, HADDR, HWRITE, HTRANS, HWDATA, output HRDATA);
  modport master(clocking CB);
endinterface

module TOP();
  bit CLK;
  always #5 CLK = ~CLK;

  AHB_IF AHBIF(CLK);
  MASTER U1 (AHBIF.master);
  SLAVE U2 (AHBIF.slave);
endmodule