library ieee;
use ieee.std_logic_1164.all;

entity XOR2 is
  port ( A, B : in std_logic;
         F : out std_logic);
end entity XOR2;

library ieee;
use ieee.std_logic_1164.all;
use work.ALL;

entity ODD_PARITY_8 is
  port ( I : in std_logic_vector (7 downto 0 );
         P : out std_logic );
end entity ODD_PARITY_8;

architecture STRUCT of ODD_PARITY_8 is
  component XOR2 is
    port ( A, B : in std_logic;
           F : out std_logic);
  end component;
  signal TEMP : std_logic_vector ( 5 downto 0);
begin
  U1 : XOR2 port map (I(0), I(1), TEMP(0));
  U2 : entity work.XOR2 port map (I(2), I(3), TEMP(1));
  U3 : entity work.XOR2 port map (I(4), I(5), TEMP(2));
  U4 : entity work.XOR2 port map (I(6), I(7), TEMP(3));
  U5 : entity work.XOR2 port map (TEMP(0), TEMP(1), TEMP(4));
  U6 : entity work.XOR2 port map (TEMP(2), TEMP(3), TEMP(5));
  U7 : entity work.XOR2 port map (TEMP(4), TEMP(5), P);
end STRUCT;