library ieee;
use ieee.std_logic_1164.all;

entity MUX is
end entity MUX;

architecture PROCESS_EQUIV of MUX is
  signal a, b, enable, sel, x, y, z : std_logic;
begin
  process (a, b, enable, sel, x, y) is
  begin
    if (enable and not sel) then
      z <= a and not b after 5 ns;
    elsif (enable and sel) then
      z <= x or y after 6 ns;
    else
      z <= '0' after 4 ns;
    end if;
  end process;
end architecture;