library ieee;
use ieee.std_logic_1164.all;

entity EN_MUX_821 is
  port (EN : in std_logic;
        S : in std_logic_vector(2 downto 0);
        D : in std_logic_vector(7 downto 0);
        O : out std_logic);
end EN_MUX_821;

architecture BEHAVE of EN_MUX_821 is
begin
  process (EN, S, D)
    variable TEMP : std_logic;
  begin
    case S is
      when "000" => TEMP := d(0);
      when "001" => TEMP := d(1);
      when "010" => TEMP := d(2);
      when "011" => TEMP := d(3);
      when "100" => TEMP := d(4);
      when "101" => TEMP := d(5);
      when "110" => TEMP := d(6);
      when "111" => TEMP := d(7);
      when others => TEMP := d(0);
    end case;
    if (EN = '0') then
      O <= TEMP;
    else
      O <= 'Z';
    end if;
  end process;
end BEHAVE;

library ieee;
use ieee.std_logic_1164.all;

entity EN_MUX_1621 is
  port (EN : in std_logic;
        S : in std_logic_vector(3 downto 0);
        d : in std_logic_vector(15 downto 0);
        O : out std_logic);
end EN_MUX_1621;

architecture STRUCT of EN_MUX_1621 is
  signal T0, T1 : std_logic;
begin
  T0 <= not S(3);
  U1: entity work.EN_MUX_821(behave)
      port map (EN => T0, S => S(2 downto 0),
                D => D(7 downto 0), O => t1);
  U2: entity work.EN_MUX_821(behave)
      port map (EN => s(3), s => S(2 downto 0),
                D => D(15 downto 8), O => T1);
  O <= T1 when EN = '0' else 'Z';
end STRUCT;