library ieee;
use ieee.std_logic_1164.all;

entity CLA_ADDER is
  port (A, B : in std_logic_vector(3 downto 0);
        S : out std_logic_vector(3 downto 0);
        C_IN : in std_logic;
        C_OUT, P, G : out std_logic);
end CLA_ADDER;

architecture BEHAVE of CLA_ADDER is
  signal PS, GS : std_logic_vector(3 downto 0);
begin
  process (A, B, C_IN)
    variable C : std_logic_vector(3 downto 0);
  begin
    S(0) <= A(0) xor B(0) xor C_IN after 5 ns ;
    PS(0) <= A(0) or B(0) after 3 ns;
    GS(0) <= A(0) and B(0) after 2 ns;
    C(0) := GS(0) or (PS(0) and C_IN);
    for i in 1 to 3 loop
      S(i) <= A(i) xor B(i) xor C(i-1) after 5 ns;
      PS(i) <= A(i) or B(i) after 3 ns;
      GS(i) <= A(i) and B(i) after 2 ns;
      C(i) := GS(i) or (PS(i) and C(i-1));
    end loop;
    C_OUT <= C(3);
    G <= GS(3) or (PS(3) and GS(2)) or (PS(3) and PS(2) and GS(1))
         or (PS(3) and PS(2) and PS(1) and GS(0));
    P <= PS(3) and PS(2) and PS(1) and PS(0);
  end process;
end BEHAVE;