library ieee;
use ieee.std_logic_1164.all;

entity seqdet_test is
end seqdet_test;

architecture test1 of seqdet_test is
	component sequence
	  port (X, CLK, RESET : in std_logic; 
	        Z : out std_logic);
  end component;
	signal XA: std_logic_vector(0 to 20) := "011011000100101101010";
	signal ZA: std_logic_vector(0 to 20) := "000000000000110000011";
	signal RESET : std_logic;
	signal CLK : std_logic := '0';
	signal X, Z : std_logic;
begin
  u1 : sequence
       port map (X => X, CLK => CLK, RESET => RESET,
                 Z => Z);
  process
  begin
    RESET <= '1', '0' after 5 ns;
    wait;
  end process;
  process (CLK)
  begin
    CLK <= not CLK after 50 ns;
  end process;
  process
    variable i : integer := 0;
    variable correct : boolean := TRUE;
  begin
    while (i <= 20) loop
      wait until CLK = '0';
      X <= XA(i);
      wait for 0 ns;
      wait until CLK = '1';
      wait for 2 ns;
      if(Z /= ZA(i)) then
        correct := FALSE;
      end if;
      i := i + 1;
    end loop;
    if (correct = TRUE) then
      report "Sequence correct";
    else
      report "Error in sequence";
    end if;
  end process;
end test1;