library ieee;
use ieee.std_logic_1164.all;

entity sequence is
  port (X : in std_logic;
        RESET : in std_logic;
        Z : out std_logic;
        CLK : in std_logic);
end sequence;

architecture behav of sequence is
  --signal window : std_logic_vector(3 downto 0);
  type state_type is (INIT, SAMPLE, EXTRA_ONE);
  signal STATE : state_type;
begin
  process(CLK)
    variable window : std_logic_vector(3 downto 0); 
  begin
    if (RESET = '1') then
      STATE <= INIT;
      Z <= '0';
    elsif (CLK'event and CLK = '1') then
      case STATE is
        when SAMPLE =>   
          window := window(2 downto 0) & X;
          if (window = "1001" or window = "0101") then
            STATE <= EXTRA_ONE;
            Z <= '1';
          else
            STATE <= SAMPLE;
            Z <= '0';
          end if;
        when EXTRA_ONE => 
          window := "0000";
          STATE <= SAMPLE;
          Z <= '1';
        when INIT =>     
          window := "0000";
          STATE <= SAMPLE;
          Z <= '0';
      end case;
    end if;
  end process;
end behav;