library ieee;
use ieee.std_logic_1164.all;

entity LHFF_S is
  port (C, L, D : in std_logic;
        Q, QB : out std_logic);
end LHFF_S;

architecture SEQ of LHFF_S is
  signal TEMP : std_logic;
begin
  process(C)
  begin
    if (C'EVENT and C = '1') then
      if (L = '1') then
        TEMP <= D;
      end if;
    end if;
  end process;
  Q <= TEMP;
  QB <= not TEMP;
end SEQ;