library ieee;
use ieee.std_logic_1164.all;

entity MAJ3 is
  generic(DEL : time);
  port (X : in std_logic_vector(2 downto 0);
        F : out std_logic);
end MAJ3;

architecture MAJ3 of MAJ3 is
begin
  F <= '1' after DEL when (X(2) = '1' and X(1) = '1') OR
                          (X(1) = '1' and X(0) = '1') OR
                          (X(2) = '1' and X(0) = '1') else
       '0' after DEL;
end MAJ3;