library ieee;
use ieee.std_logic_1164.all;

entity LHFF is
  port (C, L, D : in std_logic;
        Q, QB : out std_logic);
end LHFF;

architecture CON of LHFF is
  signal TEMP : std_logic;
begin
  A: block (not C'STABLE and C = '1')
  begin
    TEMP <= GUARDED D when (L = '1');
  end block A;
  Q <= TEMP;
  QB <= not TEMP;
end CON;

architecture SEQ of LHFF is
  signal TEMP : std_logic;
begin
  process(C)
  begin
    if (C'EVENT and C = '1') then
      if (L = '1') then
        TEMP <= D;
      end if;
    end if;
  end process;
  Q <= TEMP;
  QB <= not TEMP;
end SEQ;