library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity ADDER_32_BIT is
  port (A, B : in std_logic_vector(31 downto 0);
        CIN : in std_logic;
        COUT : out std_logic;
        C : out std_logic_vector(31 downto 0));
end ADDER_32_BIT;

architecture EXAMPLE of ADDER_32_BIT is
  component ADDER_8_BIT is
    port (A, B : in std_logic_vector(7 downto 0);
          CIN : in std_logic;
          COUT : out std_logic;
          C : out std_logic_vector(7 downto 0));
  end component;
  signal CARRY : std_logic_vector(2 downto 0);
begin
  U0: ADDER_8_BIT
      port map (A => A(7 downto 0), B => B(7 downto 0),
                C => C(7 downto 0), CIN => CIN,
                COUT => CARRY(0));
  U1: ADDER_8_BIT
      port map (A => A(15 downto 8), B => B(15 downto 8),
                C => C(15 downto 8), CIN => CARRY(0),
                COUT => CARRY(1));
  U2: ADDER_8_BIT
      port map (A => A(23 downto 16), B => B(23 downto 16),
                C => C(23 downto 16), CIN => CARRY(1),
                COUT => CARRY(2));
  U3: ADDER_8_BIT
      port map (A => A(31 downto 24), B => B(31 downto 24),
                C => C(31 downto 24), CIN => CARRY(2),
                COUT => COUT);
end EXAMPLE;