library ieee;
use ieee.std_logic_1164.all;

entity TWO_TO_FOURa is
  port (I : in std_logic_vector(1 downto 0);
        EN : in std_logic;
        O : out std_logic_vector(3 downto 0));
end TWO_TO_FOURa;

architecture CONCURRENT of TWO_TO_FOURa is
  signal TEMP : std_logic_vector(3 downto 0);
begin
  O <= "ZZZZ" when EN = '0' else
       "0001" when I = "00" else
       "0010" when I = "01" else
       "0100" when I = "10" else
       "1000" when I = "11" else
       "0000";
end CONCURRENT;

architecture SEQUENTIAL of TWO_TO_FOURa is
begin
  process(I)
    variable TEMP : std_logic_vector(3 downto 0);
  begin
    case I is
      when "00" => TEMP := "0001";
      when "01" => TEMP := "0010";
      when "10" => TEMP := "0100";
      when "11" => TEMP := "1000";
      when others => TEMP := "0000";
    end case;
    if (EN = '1') then
      O <= TEMP;
    else
      O <= "ZZZZ";
    end if;
  end process;
end SEQUENTIAL;