library ieee;
use ieee.std_logic_1164.all;

entity BARREL is
  port (D : in std_logic_vector(3 downto 0);
        CLK, LOAD, CLR, DIR : in std_logic;
        S : in std_logic_vector(1 downto 0);
        Q : out std_logic_vector(3 downto 0));
end BARREL;

architecture BARREL of BARREL is
  signal TEMP : std_logic_vector (3 downto 0);
begin
  process (CLK)
  begin
    if (CLK'event and CLK = '1') then
      if (CLR = '0') then
        TEMP <= "0000";
      elsif (LOAD = '1') then
        TEMP <= D;
      elsif (DIR = '0') then
        case S is
          when "00" => TEMP <= TEMP;
          when "01" => TEMP <= TEMP(2 downto 0) & '0';
          when "10" => TEMP <= TEMP(1 downto 0) & "00";
          when "11" => TEMP <= TEMP(0) & "000";
          when others => TEMP <= TEMP;
        end case;
      else
        case S is
          when "00" => TEMP <= TEMP;
          when "01" => TEMP <= '0' & TEMP(3 downto 1);
          when "10" => TEMP <= "00" & TEMP(3 downto 2);
          when "11" => TEMP <= "000" & TEMP(3);
          when others => TEMP <= TEMP;
        end case;
      end if;
      if (S(1)&S(0) = "01") then
        null;
      end if;
    end if;
  end process;
  Q <= TEMP;
end BARREL;