library ieee;
use ieee.std_logic_1164.all;

entity TFF is
  generic (TPCPQ, TPTQ : time);
  port (CLEAR, PRESET, CLK, T : in std_logic;
        Q, QB : out std_logic);
end TFF;

architecture BEHAV of TFF is
  signal TEMP : std_logic;
begin
  process(CLK)
  begin
    if (CLK = '0' and CLK'event) then
      if (CLEAR = '1') then
        TEMP <= '0' after TPCPQ;
      elsif (PRESET = '1') then
        TEMP <= '1' after TPCPQ;
      elsif (T = '1') then
        TEMP <= not TEMP after TPTQ;
      else
        TEMP <= TEMP;
      end if;
    end if;
  end process;
  Q <= TEMP;
  QB <= not TEMP;
end BEHAV;