entity prob is
  port (D : inout bit);
end prob;

architecture prob of prob is
  signal A, B, C, E, F : bit;
begin
  P1: process(A,C)
  begin
    B <= A after 2 ns;
    E <= C after 7 ns;
  end process P1;
  C <= A and B after 6 ns;
  P2: process(C,E)
  begin
    F <= C and E after 4 ns;
  end process P2;
  D <= A or B or C or F;
end prob;