library ieee;
use ieee.std_logic_1164.all;

entity S74194 is
  port (CLRB : in std_logic;
        CLK : in std_logic;
        S1, S0 : in std_logic;
        SDR, SDL : in std_logic;
        D : in std_logic_vector(3 downto 0);
        Q : out std_logic_vector(3 downto 0));
end S74194;

architecture BEHAV of S74194 is
  signal TEMP : std_logic_vector(3 downto 0);
begin
  process(CLRB, CLK)
  begin
    if (CLRB = '0') then
      TEMP <= "0000";
    elsif (CLK'event and CLK = '1') then
      if (S1 = '1' and S0 = '1') then
        TEMP <= D;
      elsif (S1 = '1' and S0 = '0') then
        TEMP <= SDR & TEMP(3 downto 1);
      elsif (S1 = '0' and S1 = '1') then
        TEMP <= TEMP(2 downto 0) & SDL;
      end if;
    end if;
  end process;
  Q <= TEMP;
end BEHAV;