library ieee;
use ieee.std_logic_1164.all;

entity MUX2_1 is
  port (I1, I0, SEL : in std_logic;
        F : out std_logic);
end MUX2_1;

architecture CONCURRENT of MUX2_1 is
begin
  F <= I1 when SEL = '1' else
       I0 when SEL = '0';
end CONCURRENT;