library ieee;
use ieee.std_logic_1164.all;

entity DD_FF is
  port (D, R, CLK : in std_logic;
        Q, QB : out std_logic);
end DD_FF;

architecture BEHAV of DD_FF is
  signal QTEMP : std_logic;
begin
  process (R, CLK)
  begin
    if (R = '0') then
      QTEMP <= '0';
    elsif (CLK'event) then
      QTEMP <= D;
    end if;
  end process;
  Q <= QTEMP;
  QB <= not QTEMP;
end BEHAV;