library ieee;
use ieee.std_logic_1164.all;

entity address_decoder is
  port (ADDRESS : in std_logic_vector;
        CHECK : in std_logic_vector(5 downto 0);
        SEL : out std_logic);
end ADDRESS_DECODER;

architecture BEHAV of ADDRESS_DECODER is
  alias ADDR : std_logic_vector(ADDRESS'length-1 downto 0) is ADDRESS;
begin
  process(ADDR, CHECK)
   variable MATCH : boolean;
  begin
    MATCH := TRUE;
    for I in ADDR'length-1 downto ADDR'length-1-5 loop
      if ((ADDR(I) /= CHECK(I-2)) and (CHECK(I-2) /= '-')) then
        MATCH := FALSE;
      end if;
    end loop;
    if (MATCH) then
      SEL <= '1';
    else
      SEL <= '0';
    end if;
  end process;
end BEHAV;